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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICV_PMR, Virtual Machine Priority Mask Register</h1><p>The GICV_PMR characteristics are:</p><h2>Purpose</h2>
        <p>This register provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE.</p>

      
        <div class="note"><span class="note-header">Note</span><p>Higher interrupt priority corresponds to a lower value of the Priority field.</p></div>
      
        <p>This register corresponds to the physical CPU interface register <a href="ext-gicc_pmr.html">GICC_PMR</a>.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICV_PMR are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when the GIC implementation supports interrupt virtualization.</p>

      
        <p>The Priority field of this register is aliased to <a href="ext-gich_vmcr.html">GICH_VMCR</a>.VMPR, to enable state to be switched easily between virtual machines during context-switching.</p>
      <h2>Attributes</h2>
        <p>GICV_PMR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="24"><a href="#fieldset_0-31_8">RES0</a></td><td class="lr" colspan="8"><a href="#fieldset_0-7_0">Priority</a></td></tr></tbody></table><h4 id="fieldset_0-31_8">Bits [31:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_0">Priority, bits [7:0]</h4><div class="field"><p>The priority mask level for the virtual CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.</p>
<p>If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows:</p>
<ul>
<li>For 128 supported levels, bit [0] = <span class="binarynumber">0b0</span>.
</li><li>For 64 supported levels, bits [1:0] = <span class="binarynumber">0b00</span>.
</li><li>For 32 supported levels, bits [2:0] = <span class="binarynumber">0b000</span>.
</li><li>For 16 supported levels, bits [3:0] = <span class="binarynumber">0b0000</span>.
</li></ul>
<p>For more information, see <span class="xref">'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICV_PMR</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-icc_pmr.html">ICC_PMR</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-icc_pmr_el1.html">ICC_PMR_EL1</a> provides equivalent functionality.
</li></ul>
      <h4>GICV_PMR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual CPU interface</td><td><span class="hexnumber">0x0004</span></td><td>GICV_PMR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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